Sampling rates of analog-to-digital converters (ADC) are generally increasing. For example, as analog sensing equipment with increased resolution becomes available, ADC sampling rates may increase to handle greater quantities of data from the analog sensing equipment. At higher sampling rates (e.g., sampling rates of 200 MHz or more) capturing an output signal from an ADC at an appropriate time may be more important. For example, the ADC's output signal may change in response to an analog input signal and may be briefly unstable. Storing the ADC's output signals at an unstable period may result in storing inaccurate data values. For example, a data register may register an output of the ADC upon receiving a triggering edge (e.g., a leading edge or a trailing edge) of a clock signal. If the triggering edge of the clock signal is received when the output of the ADC is in transition, a data value registered at the data register may be skewed.
Sampling of the ADC's output signal may be manually tuned by examining registered data for potentially erroneous stored values. However, as sampling rates increase, stable intervals of the ADC output signal may decrease making manual tuning more difficult and more time consuming.